The present invention relates to monitoring bit error rate (BER), and more particularly relates to monitoring high-speed serializer-deserializer (SerDes) link channels and based on the monitoring, adjusting adaptive equalization settings, if possible, to improve channel or link processing.
System architectures such as Infiniband and PCI Express utilize high-speed serializer-deserializer (SerDes) links to transmit data packets across serial links. These architectures are migrating to SerDes links that support link speeds at single data rate (SDR), double data rates (DDR) and quad data rates (QDR). In doing so, each architecture defines and provides for link-training methods that enable a high-speed SerDes link to support transmitting data at the higher data rates. One such architecture, Infiniband, provides for link operation at such higher data rates.
The Infiniband specification, Vol. 2, Rel. 1.2, supports adaptive equalization to compensate for signal distortion at the higher data rates. The Infiniband specification, section 5.6.4, Link Training State Machine, defines a procedure to enable adaptive equalization in the Infiniband system. The Link Training State Machine specification defines a 2 ms period to negotiate each side of a link's capabilities to support the SDR, DDR and QDR speeds. Once the negotiation process is completed, the Infiniband specification defines a 100 ms period to allow the default, or any of the 16 other possible (possibly available) adaptive equalization settings to be implemented across the entire link width, i.e., all of the link channels.
This solution is limited, however, in that one setting is selected for the entire link width (i.e., all of the channels). Link widths can be 1, 4, 8 and 12 channels wide using the Infiniband architecture, and up to 16 channels wide for the PCI express link architecture. In an ideal SerDes link system, every channel would be uniform and the above-mentioned method would be fine. In reality, however, this is hardly the case. That is, each medium or channel comprising the link has it own set of impedance characteristics and tolerances. The Link Training State Machine method (Infiniband) does not take into the account the varying characteristics between each channel. By limiting each channel to one set of adaptive equalization settings, some of the channels are not optimized at DDR/QDR speeds. For example, at DDR/QDR speeds, real-time operation may find that only 8 channels out of the 12 available channels in an Infiniband design are operating effectively, which would result in a significant performance degradation.
What would be desirable, therefore, is a new structure and process that allows for each channel within a high-speed Infiniband or PCI Express architecture to be independently monitored for BER, and allows the channel's adaptive equalization setting to be modified where necessary to adjust the BER in the channel in accordance with the monitored BER.